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Communication Dans Un Congrès Année : 2011

3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology

Résumé

In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

Domaines

Electronique
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Dates et versions

hal-00665170 , version 1 (01-02-2012)

Identifiants

  • HAL Id : hal-00665170 , version 1

Citer

Dominique Houzet, Mohamad Jabbar, Omar Hammami. 3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology. IP-Embedded System Conference and Exhibition (IP-SoC 2011), Dec 2011, Grenoble, France. pp.1. ⟨hal-00665170⟩
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