A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time Sigma Delta ADC for a Digital Closed-Loop Class-D Amplifier

A. Donida , Rémy Cellier (1) , A. Nagari , P. Malcovati (2) , A. Baschirotto

1 INL - CSH - INL - Conception de Systèmes Hétérogènes
2 Department of Electrical Engineering

This paper presents a continuous-time third-order modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed Sigma Delta modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V Sigma Delta modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.

Mots clés: Sigma-delta modulation; Audio systems; Amplifiers; Analog-digital integrated circuits

Domaines: Sciences de l'ingénieur [physics]; Optique / photonique; Matériaux; Micro et nanotechnologies/Microélectronique

A. Donida, Rémy Cellier, A. Nagari, P. Malcovati, A. Baschirotto. A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time Sigma Delta ADC for a Digital Closed-Loop Class-D Amplifier. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015, 62 (3), pp.645-653. ⟨10.1109/TCSI.2014.2373971⟩. ⟨hal-01489399⟩