A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders

Fabrice Lozachmeur (1, 2) , Arnaud Tisserand (1)

1 Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools
2 THALES [France]

The paper presents an instruction set extension for the CV32E40P RISC-V processor core to protect cryptosystems against side channel attacks using masking at high orders. A first masking order is fixed in hardware at synthesis time. Then a higher masking order is obtained using software composition over the hardware one. The solution has been implemented, validated and evaluated in FPGA.

Keywords: hardware security; side-channel attack; countermeasure; processor instruction set extension

Domains: Cryptography and Security [cs.CR]

Fabrice Lozachmeur, Arnaud Tisserand. A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders. 66th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2023) "Reinventing Microelectronics", Aug 2023, Phoenix, AZ, United States. ⟨hal-04132900⟩